1. Field of the Invention
The present invention relates to a bus controller and an information processing device for performing control of the interface with an external bus at a high speed, with respect to a request for the use of the external bus.
2. Description of the Related Art
The performance of a semiconductor device such as a microcontroller and a microprocessor has been increasing as miniaturization and high speed circuitry of semiconductors have been developed. The promotion of the higher performance of the semiconductor is accompanied by higher speed of operation frequency of the semiconductor device. Among semiconductor devices, some operate at an operation frequency of several 100 MHz.
On the other hand, the operation frequency of the entire system employing the semiconductor device such as a microcontroller and a microprocessor is only about several 10 MHz. This is because it is necessary to consider various factors such as a signal delay between devices, operation rates of other devices, low power consumption, and the prevention of the generation of noises. For this reason, the semiconductor device such as a microcontroller and a microprocessor generally includes a frequency synthesizer such as PLL (Phase Locked Loop) inside the semiconductor device. The frequency synthesizer generates a high speed internal clock signal having a frequency several times the frequency of an external clock signal, and the high internal clock signal is used inside the semiconductor device.
A bus controller for controlling one or more external devices connected to an external bus to access the external bus is known in the art. The bus controller controls an access of the external device to the external bus in accordance with an access request from a processor.
The external device is classified into a synchronous external device and an asynchronous external device. The synchronous external device operates in synchronization with an external clock signal. The asynchronous external device does not require a clock signal input and operates in asynchronization with the clock signal.
In the case of the synchronous external device, the bus controller included in the processor generally generates an access controlling signal in synchronization with the external clock signal, and the access controlling signal is supplied to the synchronous external device so that the bus interface between the processor and the synchronous external device is controlled.
In the case where both of the synchronous external device and the asynchronous external device are connected to the same external bus, it may be assumed that the bus interface between the processor and the external device is controlled in the following manner: under the condition that a requirement necessary for the access controlling signal to access the asynchronous external device (e.g., a requirement regarding a timing at which the access controlling signal enters into a low level from a high level) is satisfied, a common access controlling signal generated in synchronization with the external clock signal is supplied to the both of the synchronous external device and the asynchronous external device. Such control of the bus interface is performed with no problems, in the case where the frequency of the external clock signal and the frequency of the internal clock signal are substantially equal. However, in the case where the frequency of the internal clock signal is higher than the frequency of the external clock signal, such control of the bus interface causes a problem that the start of the access to the asynchronous external device is delayed. This is because, since the access controlling signal for the asynchronous external device is generated in synchronization with the external clock signal, an idle cycle for waiting for synchronization with the external clock signal occurs.
Hereinafter, the operation of the asynchronous external device in the case where the common access controlling signal generated in synchronization with the external clock signal is supplied to both of the synchronous external device and the asynchronous external device will be described with reference to FIG. 7. The frequency of the internal clock signal used inside the processor is assumed to be four times the frequency of the external clock signal.
In FIG. 7, reference numeral 100 denotes an external clock signal, reference numeral 101 denotes an internal clock signal, reference numeral 102 denotes an address output from a CPU to a bus controller, reference numeral 103 denotes a read request signal output from the CPU to the bus controller, reference numeral 104 denotes a write request signal output from the CPU to the bus controller, reference numeral 105 denotes data which is input and output between the CPU and the bus controller, reference numeral 116 denotes a data response signal output from the bus controller to the CPU, reference numeral 120 denotes a chip select signal (hereinafter, referred to as an "NCS signal") indicating an external bus cycle period, reference numeral 121 denotes an output enable signal (hereinafter, referred to as an "NOE signal"), reference numeral 122 denotes a write enable signal (hereinafter, referred to as an "NWE signal"), reference numeral 123 denotes an external address bus, and reference numeral 124 denotes an external data bus.
In a cycle i1, the CPU makes a request for a read operation to the bus controller. The request for the read operation is made in such a manner that the CPU outputs the address 102 to the bus controller and the CPU asserts the read request signal 103. The asserted read request signal 103 is at a low level. The bus controller performs a synchronization process with the external clock signal 100, and starts an external bus cycle from a cycle e1 of the external clock signal 100.
During the period of the external bus cycle, the bus controller outputs a value of the address 102 to the external address bus 123, and asserts the NCS signal and the NOE signal. The asserted NCS signal and the NOE signal are at a low level. The external bus cycle autonomically ends depending on the number of cycles set in a register inside the processor. For example, the number of cycles of the example shown in FIG. 7 is one cycle.
In a period during which the NOE signal is being asserted (i.e., cycles i5, i6 and i7), data is read from the external device to the external data bus 124. The data is captured by the processor at the end of the cycle e1 (the end of the cycle i7).
In a cycle i8, the data response signal 116 is asserted, and data is supplied to the CPU. Thus, the read operation is completed.
In a cycle i10, the CPU makes a request for a write operation to the bus controller. The request for the write operation is made in such a manner that the CPU outputs the address 102 to the bus controller and the CPU asserts the write request signal 104. The asserted write request signal 104 is at a low level. The bus controller performs a synchronization process with the external clock signal 100, and starts an external bus cycle from a cycle e3 of the external clock signal 100.
During the period of the external bus cycle, the bus controller outputs a value of the address 102 to the external address bus 123, and asserts the NCS signal and the NWE signal. The asserted NCS signal and the NWE signal are at a low level. The external bus cycle autonomically ends depending on the number of cycles set in a register inside the processor. For example, the number of cycles of the example shown in FIG. 7 is one cycle.
In a period during which the NWE signal is asserted (i.e., cycles i13 and i14), a value of the external data bus 124 is written to the external device.
In a cycle i15, the data response signal 116 is asserted. Thus, the write operation is completed.
In this manner, although it is possible for the bus controller to start external access at the cycle i2, the bus controller starts the bus cycle at the cycle i4 after waiting for synchronization with the external clock signal for two cycles (cycles i2 and i3). This is because the bus controller generates an access controlling signal in synchronization with the external clock signal.
Similarly, although it is possible for the bus controller to start an external access at the cycle i11, the bus controller starts the bus cycle at the cycle i12 after waiting for synchronization with the external clock signal for one cycle (cycle i11). This is because the bus controller generates an access controlling signal in synchronization with the external clock signal.
As described above, in the case where the ratio of the frequency of the internal clock signal to the frequency of the external clock signal is 4, a maximum of three idle cycles for waiting for synchronization occur. The number of such a synchronization wait cycle increases with increasing the ratio of the frequency of the internal clock signal to the frequency of the external clock signal. In the case where the ratio is N, a maximum of (N-1) synchronization wait cycles occur.
Furthermore, in FIG. 7, in the case where the access time of the external device is equal to three cycles of the internal clock signal, the read operation from the external device should inherently end at the cycle i6. However, the read operation from the external device actually end at the cycle i7. This is because the access to the external device is performed in a cycle unit of the external clock signal. The same is applied to the write operation to the external device.
As described above, in the case where the processor accesses the external device in synchronization with the external clock signal, idle cycles are inserted due to waiting for synchronization with the external clock signal, though the processor is ready for the external access therein. This delays the start of the access to the external device, resulting in the degradation of the performance of the entire information processing device including the processor and the external device.
As described above, in light of the development of the semiconductor technique in recent years, the difference between the frequency of the external clock signal and the frequency of the internal clock signal tends to be increasingly larger. Therefore, there is a concern that the problem of the delay of the start of accessing the external device may become serious.